To transform your ideas into designs, you must be able to simulate large circuits quickly and with a high degree of accuracy. That means you need a simulation tool that offers fast run times, integrates with your other design tools, and is compatible with industry standards. Tanner T-Spice Circuit Simulator puts you in control of simulation jobs with an easy to use graphical interface and a faster, more intuitive design environment. With key features such as device state plotting, real-time waveform viewing and analysis, and command tools for simpler SPICE syntax creation, T-Spice saves you time and money during the simulation phase of your design flow. T-Spice enables more accurate simulations by supporting the latest transistor models—including BSIM4.5 and the Penn State Philips (PSP) model. And because T-Spice is compatible with a wide range of design solutions and runs on Windows-based systems, it fits easily and cost-effectively into your current tool flow.
T-SPICE is a most powerful tool for complete circuit design and analysis. It is powerful simulation tools for almost all integrated circuits. Almost every IC can be simulated by using tanner spice. T-Spice performs fast and accurate simulation of analog and mixed
Analog/digital circuits. The simulator can analyze large, complex designs with hundreds of thousands of circuit elements. The T-Spice Advanced Model Package includes the latest and best device models available, to help you get the most realistic simulation results possible. The Advanced Model Package also includes coupled line models and support for user-defined device models via tables or C functions. The design cycle for the development of electronic circuits includes an important pre-fabrication verification phase. Because of the expense and time pressures associated with the fabrication step,
Accurate verification is crucial to an efficient design process. The role of T-Spice is to help design and verify a circuit’s operation by numerically solving the differential equations describing the circuit. T-Spice simulation results allow circuit designers to verify and fine-tune designs before submitting them for fabrication.
v Improve simulation accuracy with advanced modeling features
T-Spice provides extensive support of behavioral models using expression controlled sources, tables, and external C-code. Behavioral models give you the flexibility to create customized models of virtually any device. T-Spice also supports the latest industry models, including the transistor model recently selected as the next standard for simulating future CMOS transistors manufactured at 65 nanometers and below—the Penn State Philips (PSP) model. PSP will simplify the exchange of chip design information and support more accurate digital, analog, and mixed-signal circuit behavior analysis.
Most SPICE simulators don’t support the added extensions that foundries use. T-Spice supports foundry extensions, including HSPICE foundry extensions to models.
• Supports PSP, BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC, and MEXTRAM models.
• Includes two stress effect models, from the Berkeley BSIM4 model and from TSMC processes, in the BSIM3 model to provide more accuracy in smaller geometry processes.
• Supports gate and body resistance networks in RF modeling. • Performs non-quasi-static (NQS) modeling.
• Supports comprehensive geometry-based parasitic models for multi-finger devices.
• Models partially depleted, fully depleted, and unified FD-PD SOI devices.
• Models self-heating and RF resistor networks.
• Performs optional table-based modeling for fastest simulations.
• Includes enhanced diode and temperature equations to improve compatibility with many foundry model libraries.
T-Spice also incorporates several innovations and improvements not found in other SPICE and SPICE compatible simulators:
Ø Speed. The results of device model evaluations are stored in tables and reused. Because evaluation of device models can be computationally expensive, this technique can yield dramatic simulation speed increases. The memory used by T-Spice tables is optimized by storing only those points which are actually needed. T-Spice allows you to specify which devices use tables.
Ø Convergence. T-Spice uses advanced mathematical methods to achieve superior numerical stability. Large circuits and feedback circuits, impossible to analyze with other SPICE products, can be simulated in T-Spice.
Ø Accuracy. T-Spice uses very accurate numerical methods and charge conservation to achieve superior simulation accuracy.
Ø Advanced models. T-Spice incorporates the latest and best transmission-line and semiconductor device models to give you simulation results which are closer to real-world behavior, including the exclusive physically based Maher-Mead MOSFET.
Ø Macro modeling. T-Spice simulates circuits containing “black box” macro devices. A macro device can directly use experimental data as its device model. Macro devices can also represent complex devices, such as logic gates, for which only the overall transfer characteristics, are of interest.
Ø Input language extensions. The T-Spice input language is an enriched version of the standard SPICE language. It contains many enhancements, including parameters, algebraic expressions, and a powerful bit and bus input wave specification syntax.
Ø External model interface. Users can develop custom device models using C or C++.
Ø Runtime waveform viewing. The W-Edit waveform viewer displays graphical results during simulation. T-Spice analysis results for voltages, currents, charges, and power can be written to single or multiple files.
Ø Schematic entry. T-Spice Pro includes the schematic editor View Draw.
T-Spice maintains compatibility with traditional circuit simulation tools, while using the best available simulation technology to deliver results as quickly and accurately as possible
v Tanner Tools Design System
T-Spice Pro is part of a complete integrated circuit design tool suite for layout, verification and simulation offered by Tanner EDA.
Simulation Tools
§ T-Spice: analog/digital circuit simulator.
§ W-Edit: waveform viewer.
T-Spice offers fast and accurate simulation of analog and mixed analog/digital circuits. Full chip designs with more than 300,000 elements can be simulated. T-Spice accepts standard SPICE, table based, and user-defined models. The Advanced Model Package includes most current models, such as BSim3v3. Tanner EDA offers an optional process characterization service to extract parameters for all T-Spice-supported models. W-Edit streamlines and customizes the task of graphical data presentation. It accepts data files without modification from T-Spice.
v Define a Project
Dashboard is used to organize data related to a design project. Dashboard functions as the project manager and the launch pad for all other ePD and T-Spice Pro applications.
The Dashboard contains a tree control of toolboxes, which are folders containing related
application programs. To begin a project using View Draw you must define a project, associate it with a design, and specify the libraries that the design will be using. A project is simply a directory that identifies your current working area. The project directory
References or contains all of the component libraries used in your schematics, as well as other files and subdirectories associated with your design. The Project Wizard provides a simple way to create a new project and set up your initial library search order.
Library Setup and Search Order
The library search order specifies the list of libraries from which you will select component symbols for a particular project. When you create a schematic, you build the design from component symbols. These may include standard parts libraries supplied with your software, user-defined components and symbols, or third-party vendor libraries. They may reside on your local workstation or in a network location. There are three pieces of information you use in order to specify libraries in your library search order: the library directory path, the library type (read-only, writable, or mega file), and optionally a library alias.
Run Circuit Analysis
Use the T-Spice circuit simulator for operating point, time domain, swept frequency, and swept DC simulations. The T-Spice Advanced Model Package includes additional modeling features such as coupled line models and support for user-defined device models via tables or C functions.
Waveform Viewing
Use the W-Edit waveform viewer to view T-Spice simulation output waveforms as they are being generated during simulation.
v Perform sophisticated analysis
T-Spice uses superior numerical techniques to achieve convergence for circuits that are often impossible to simulate with other SPICE programs. The types of circuit analysis it performs include:
• DC and AC analysis.
• Transient analysis with Gear or trapezoidal integration.
• Enhanced noise analysis.
• Monte Carlo analysis over unlimited variables and trials.
• Virtual measurements with functions for timing, error, and statistical analysis.
• Parameter sweeping using linear, log, discrete value, or external file data sweeps.
With T-Spice, you can:
• Optimize designs with variables and multiple constraints and goals.
• Achieve performance goals by applying a Levenberg-Marquardt non-linear optimizer.
• Use plot statements that support wildcards.
• Use plot statements and parameter definitions that support mathematical expressions involving C-style math functions.
• Use bit and bus logic waveform inputs.
v Simulation Concepts
Simulation Algorithms
T-Spice is designed to solve a wide variety of circuit problems. Its flexibility is due to robust algorithms which can be optimized by means of user-adjustable parameters.
Kirchoff’s Current Law.
T-Spice uses Kirchoff’s Current Law (KCL) to solve circuit problems. To T-Spice, a circuit is a set of devices attached to nodes. The circuit’s state is represented by the voltages at all the nodes. T-Spice solves for a set of node voltages that satisfies KCL (implying that the sum of the currents flowing into each node is zero). In order to evaluate whether a set of node voltages is a solution, T-Spice computes and sums all the
Currents flowing out of each device into the nodes connected to it (its terminals). The relationship between the voltages at a device’s terminals and the currents through the terminals is determined by the device model. For example, the device model for a resistor of resistance R is i = Δv ⁄ R, where Δv represents the voltage difference across the device.
DC Analysis
Most T-Spice simulations start with a DC operating point calculation. A circuit’s DC operating point is its steady state, which would in principle be reached after an infinite amount of time if all inputs were held constant. In DC analysis, capacitors are treated as open circuits and inductors as short circuits. Because many devices, such as transistors, are described by nonlinear device models, the KCL equations that T-Spice solves in DC
analysis are nonlinear and must therefore be solved by iteration. On each iteration, T-Spice tries to find a set of node voltages that satisfies KCL more closely than the previous set. When the KCL equations are satisfied “well enough” (the sums of currents into nodes
are small enough), the process stops. The abstol and reltol options determine how closely KCL must be satisfied. The numnd option imposes a limit on the number of iterations. If numnd iterations are reached without a solution being found, then non convergence is declared.
Transient Analysis
In transient analysis, T-Spice solves for a circuit’s behavior over some time interval. In this mode, T-Spice takes small time steps, solving for the circuit’s state at each step. At each time step, two approximations are made.
First, a small error — the discretization error — is introduced because T-Spice cannot take infinitely small time steps. The chargetol and relchargetol options determine the acceptable limits of discretization error. In general, taking smaller time steps decreases the discretization error, so tightening the tolerances has the effect of higher accuracy at the expense of smaller time steps and therefore longer simulation times and larger output files. The discretization error is also affected by the order of the time integration method used, adjusted with the maxord option.
Second, just as in DC analysis, T-Spice solves the nonlinear KCL equations iteratively at each time step. The accuracy is affected by an iteration stopping criterion. The same tolerances as in DC analysis — abstol and reltol —affect this solution process.
v Device Model Evaluation
T-Spice can evaluate device models with any of the following methods. Direct model evaluation is the default.
Evaluation Methods
! In direct model evaluation, data points (the charges and currents at device terminals) are computed “directly” at each step from terminal voltages using analytical model equations. This method typically produces the most accurate results, but also typically takes the most time, because values must be repeatedly recomputed from very complex equations.
! In table-based model evaluation, data points are read or interpolated from precomputed tables stored in memory. When the simulation requires the charge or current value (output) corresponding to a given voltage (input) for a particular device, T-Spice uses the voltage to look up the appropriate value in the device table, interpolating if necessary to arrive at the needed charge or current. This method is considerably faster than direct model evaluation. By default, T-Spice uses analytical models to generate cached, or internal, tables for use during a simulation. At the conclusion of the simulation these internal tables are discarded.
v Parametric Analysis
Under many circumstances, T-Spice will be required to study the effects on circuit performance of variations in parameter values. For example, parametric analysis can be
used to evaluate multidimensional trends in the output over defined ranges of input
values or the sensitivity of circuit behavior to random fluctuations in fabrication conditions. A large range of parameters may be systematically and automatically varied:
! External parameters (such as temperature)
! Simulation parameters (such as tolerances)
! Device parameters (such as input voltage level)
! Model parameters (such as transistor length)
Three types of parametric analysis are made possible by T-Spice: parameter sweeping, Monte Carlo analysis, and optimization.
Monte Carlo Analysis
Monte Carlo analysis generates “random” variations in parameter values by drawing them probabilistically from a defined distribution. For each value thus chosen, all analyses requested by the input file are performed, and the results recorded. Monte Carlo analysis is performed using the keyword sweep;
Syntax
.step sweep [[sweep] sweep [[sweep] sweep]]
Where sweep is in one of the following formats:
[lin] variable start stop inc
or
decoct variable start stop npoints
or
variable lindecoct npoints start stop
or
variable list value [value […]]
or
list variable value [value […]]
or
variable poi npoints [value […]]
or
data=dataname
or
monte=mcruns [seed=seedval]
or
optimize=optname results=measname [measname […]] model=optmodelname
This example demonstrates Monte Carlo Analysis on a CMOS inverter circuit.
Input
...
* Main circuit: invert5
c2 out Gnd 800ff
.include ml2_125mc.md
m1n out in Gnd Gnd nmos L=5u W=8u
m1p out in Vdd Vdd pmos L=5u W=12u
.measure tran falltime trig v(out) val=2.8 fall=1 targ v(out) val=0.2 fall=1
.param vto_n=unif(0.622490, 0.5, 1) vto_p=unif(-0.63025, 0.5, 1)
.tran 2n 600n sweep monte=10
.print tran in out
vdd Vdd Gnd 3.0
vin in Gnd pwl (0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V 300ns
+ 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V)
* End of main circuit: invert5
A Monte Carlo analysis sweeps parameter values that are chosen based on statistical variations. In this example, T-Spice varies the model parameter vto using random values chosen by probability distribution. In model file ml2_125mc.md, the .model statement specifies the vto parameter as two variables: vto_n for an n-channel MOSFET and vto_p for a p-channel MOSFET.
Input invert5.cir
Output invert5.out
The .param statement defines the probability distribution, where vto_n=unif(0.622490, 0.5, 1) and vto_p=unif(-0.63025, 0.5, 1) select uniform distributions centered at 0.622490 and -0.63025 with relative variation of 50%. The keyword monte=10 in the .tran statement invokes Monte Carlo analysis with 10 runs. The .measure statement measures the falltime of the output pulse for different values of vto.
Output
T-Spice reports the transient analysis results in ten sections for the ten Monte Carlo runs.
Following is part of the output section for the first run.
TRANSIENT ANALYSIS - Monte-Carlo-index=1
Time
0.0000e+000 0.0000e+000 2.9996e+000
6.0000e-010 0.0000e+000 2.9996e+000
2.6000e-009 0.0000e+000 2.9996e+000
4.6000e-009 0.0000e+000 2.9996e+000
6.6000e-009 0.0000e+000 2.9996e+000
8.5999e-009 0.0000e+000 2.9996e+000
…
Measurement results are reported at the end of each section.
MEASUREMENT RESULTS - Monte-Carlo-index=1
falltime = 1.2278e-008
Trigger = 1.0471e-007
Target = 1.1699e-007
At the end of the output file, T-Spice reports the Monte Carlo values for each run The measurement results are summarized along with statistical results from the analysis (minimum, maximum, mean, average deviation, variance, and sigma).
MONTE CARLO PARAMETER VALUES
Index 1
parameter Vto for model nmos = 3.1202e-001
parameter Vto for model pmos = -6.7032e-001
Index 2
parameter Vto for model nmos = 4.3157e-001
parameter Vto for model pmos = -8.2483e-001
Index 3
parameter Vto for model nmos = 6.7541e-001
parameter Vto for model pmos = -6.1756e-001
…
TRANSFER ANALYSIS
Index<> falltime<>
1.0000e+000 1.1738e-008
2.0000e+000 1.2477e-008
3.0000e+000 1.4346e-008
4.0000e+000 1.3173e-008
5.0000e+000 1.5912e-008
6.0000e+000 1.2399e-008
7.0000e+000 1.5150e-008
8.0000e+000 1.2944e-008
9.0000e+000 1.2069e-008
10.0000e+001 1.2278e-008
Minimum 1.1738e-008
Maximum 1.5912e-008
Mean 1.3249e-008
Avg dev 1.1325e-009
Variance 1.9941e-018
Sigma 1.4121e-009
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